p0 ESC p 0 proportional off S0ESC S 0 superscript on AESC A 7 line-distance 7/72 (at 9-pin=ok) or 7/60 (at 24-pin=wrong) +#ESC + 35 line-distance 35/360 at Epson-24-pin (not at Canon BJ) 1ESC 1 line-distance 7/72 at Canon BJ and 9-pin (not at Epson-24-pin) tested with: - 9-pin Epson FX 80 (CBM MPS 1230) - 9-pin IBM proprinter (CBM MPS 1230) - 24-pin Epson LQ 860 (Panasonic 2123) - 24-pin IBM proprinter X24E (Panasonic 2123) - Canon BJ (Canon BJC 220) Put this text without any change to a 9- or 24-pin- or an Epson-compatible ink-jet-printer. Don't use a wordprocessor. Better is a simple editor. this paper-sheet is waste C64 IECOUT = (1541 IECIN) (and SAVE)========================================= fc33 *lda $dd00 4 reads bus (41:fbd8) lda $dd00 IA> fc36 *bpl $fc33 2/3 waits until 1541 sets data = inactive bpl $fc33 IA- - IA- fc38 *and #$07 2 mascs bit 2-0 =pin M of userport & VIC bank and #$07 IA- - IA- fc3a *sta $95 3 saves pinM&VICbank (stores it to IECOUTbyte) sta $95 IA- - IA- - IA- fc3c *sec 2 sec IA- - IA- fc3d *lda $d012 4 VIC rasterbar lda $d012 IA- - IA- - IA- - IA- fc40 *sbc $d011 4 bit 2-0 = vertical softscroll register sbc $d011 IA- - IA- - IA- - IA- fc43 *and #$07 2 mascs bit 2-0, that 8 rasterbars remain and #$07 IA- - IA- fc45 *cmp #$06 2 cmp #$06 IA- - IA- fc47 *bcs $fc3d 2/3 b.i. too few time until next badline bcs $fc3d IA- - IA- fc49 *lda $95 3 (bus port byte) lda $95 IA- - IA- - IA- fc4b *sta $dd00 4 data=inactive,clock=inactive,ATN=inactive sta $dd00 IA- - (41:fbdb) IA- - IA- - put here 1541-paper-arrow(early/late)----------II> fc4e *pla 4 high nibble of IECOUT byte pla II- - II- - II- - II- fc4f *ora $95 3 restores pin M & VIC-bank ora $95 II- - II- - II- fc51 *sta $dd00 4 bit5->data-out, bit4->clock-out (41:fbe2) sta $dd00 II- - II- - II- - ----54> fc54 *lsr 2 lsr 54- - 54- fc55 *lsr 2 lsr 54- - 54- fc56 *and #$f0 2 masks off ATN, pin M, VIC bank and #$f0 54- - 54- fc58 *ora $95 3 restores pin M & VIC bank ora $95 54- - 54- - 54- fc5a *sta $dd00 4 bit7->data-out, bit6->clock-out (41:fbe8) sta $dd00 54- - 54- - 54- - ----76> fc5d *lda $fc8a,x 4 table of low nibbles lda $fc8a,x 76- - 76- - 76- - 76- fc60 *ora $95 3 restores pin M & VIC-bank ora $95 76- - 76- - 76- fc62 *sta $dd00 4 bit1->data-out, bit3->clock-out (41:fbf0) sta $dd00 76- - 76- - 76- - ----13> fc65 *lsr 2 lsr 13- - 13- fc66 *lsr 2 lsr 13- - 13- fc67 *and #$f0 2 masks off ATN, pin M, VIC bank and #$f0 13- - 13- fc69 *ora $95 3 restores pin M & VIC bank ora $95 13- - 13- - 13- fc6b *sta $dd00 4 bit0->data-out, bit2->clock-out (41:fbf6) sta $dd00 13- - 13- - 13- - ----02> fc6e *and #$0f 2 (data=inactive,clock=inactive) and #$0f 02- - 02- fc70 *bit $a3 3 flag for EOI bit $a3 02- - 02- - 02- fc72 *bmi $fc76 2/3 b.i. EOI bmi $fc76 02- - 02- fc74 *ora #$10 2 (clock=active) ora #$40 02- - 02- fc76 *sta $dd00 4 data=I clock=I (noEOI) / A (EOI) (41:fc00) sta $dd00 02- - 02- - 02- - ----I?> fc79 *pla 4 pla I?- - I?- - I?- - I?- fc7a *tax 2 restores x tax I?- - I?- fc7b *lda $95 3 restores pin M & VIC-bank lda $95 I?- - I?- - I?- fc7d *ora #$10 2 (clock=active) ora #$10 I?- - I?- fc7f *sta $dd00 4 clock=active sta $dd00 I?- - I?- - I?- - ----IA> fc82 *bit $dd00 4 reads bus bit $dd00 IA- - IA- - IA- - ----IA> (C64 IECOUT) = 1541 IECIN (and SAVE)========================================= -AI fbd8 *sta $1800 4 data=inactive, clock=inactive, ATNackn=inactive -AI a=#00 if C64 sets clock=inactive (=error) -AI a=#04 if C64 sets clock=active (=ok) (64:fc36) -II -II -II -II -II -II -II -II -II -II 1541 waits some loops -II until C64 calculates its badline -II -II -II -II -II -II -II -II -II fbdb *bit $1800 4 reads bus (64:fc4b) -II -II for 0.1uS branches 3uS -II fbdb *bit $1800 4 reads bus (64:fc4b) -II -II exactly no branch 2uS -II fbe0 *pha 3 delay -II -II -II fbe1 *pla 4 delay -II -II -II -II fbe2 *lda $1800 4 reads bus (64:fc51) -II -II C64 1541 C64 1541 bit0 bit4=clock->bit2 -II fbe5 *asl 2 bit0->bit1 bit2->bit3 -II -II fbe6 *pha 3 delay -II -II -II fbe7 *pla 4 delay -II -II -II -II fbe8 *ora $1800 4 bus (64:fc54) -II -II C64 1541 C64 1541 bit0 bit6=clock->bit2 -II fbeb *and #$0f 2 mascs bit 3-0 -II -II fbed *tax =highnibble of C64-IECOUT byte -II -II fbee *ldy $7a 3 =#$00 (flag for TALK) -II (not ldy #$00 because of timing: 3uS instaed of 2uS)? -II -II fbf0 *lda $1800 4 reads bus (64:fc62) -II -II C64 1541 C64 1541 bit0 bit3=clock->bit2 -II fbf3 *asl 2 bit0->bit1 bit2->bit3 -II -II fbf4 *pha 3 delay -II -II -II fbf5 *pla 4 delay -II -II -II -II fbf6 *ora $1800 4 bus (64:fc68) -II -II C64 1541 C64 1541 bit0 bit2=clock->bit2 -II fbf9 *and #$0f 2 mascs bit 3-0 -II -II fbfb *ora $fc13,x 4 table for highnibble -II -II -II -II fbfe *sta $85 3 1541 IECIN byte -II -II -II fc00 *lda 1800 4 reads bus (64:fc76) -II -II fbb7 *cmp #$40 2 %01000000 cmp #$40 AI- - AI- fbb9 *bcc $fbb4 2/3 waits until 1541 sets clock = inactive bcc $fbb4 AI- - AI- fbbb *and #$07 2 mascs bit 0-2 (pin M & VIC-banc) and #$07 AI- - AI- fbbd *pha 3 saves pin M & VIC-banc to stack pha AI- - AI- - AI- fbbe *lda $d012 4 VIC rasterbar (carry is set) lda $d012 AI- - AI- - AI- - AI- fbc1 *sbc $d011 4 bit 2-0 = vertical softscroll register sbc $d011 AI- - AI- - AI- - AI- fbc4 *and #$07 2 mascs bit 2-0, that 8 rasterbars remain and #$07 AI- - (data=inactive,clock=inactive,ATN=inactive) AI- fbc6 *cmp #$07 2 cmp #$07 AI- - AI- fbc8 *bcs $fbbe 2/3 b.i. too few time until next badline bcs $fbbe AI- - AI- + + + (7 uS only that timing fits, if + + C64 doesn't wait at badline-loop + + and 1541 doesn't make waiting-loop + + at ffb8 at all) + + + + + fbca *pla 4 restores pin M and VIC-banc pla AI- - AI- - AI- - AI- fbcb *sta $dd00 4 data=inactive,clock=inactive,ATN=inactive sta $dd00 AI- - (41:ffb8) AI- - AI- - (2) put 1541 paper arrow here (late/ealy) ----II> fbce *sta $a4 3 saves it (to IECIN byte) sta $dd00 II- - II- - II- fbd0 *ora #$20 2 (data=active) ora #$20 II- - II- fbd2 *pha 3 saves to stack pha II- - II- - II- fbd3 *nop 2 nop II- - II- fbd4 *nop 2 nop II- - II- fbd5 *ora $dd00 4 reads bus (41:ffbd) ora $dd00 II- - II- - 1541 C64 1541 C64 II- - bit1=data->bit7 bit0=clock->bit6 ----II> fbd8 *lsr 2 bit7->bit6 bit6->bit5 lsr II- - II- fbd9 *lsr 2 bit6->bit5 bit5->bit4 lsr II- - II- fbda *nop 2 nop II- - II- fbdb *ora $dd00 4 reads bus (41:ffc4) ora $dd00 II- - II- - 1541 C64 1541 C64 II- - bit3=data->bit7 bit2=clock->bit6 ----II> fbde *lsr 2 bit7->bit6 bit6->bit5 5->4 4->3 lsr II- - II- fbdf *lsr 2 bit6->bit5 bit5->bit4 4->3 4->2 lsr II- - II- fbe0 *eor $a4 3 inverts bit 2-0 pin M & VIC-banc eor $a4 II- - II- - II- fbe2 *eor $dd00 4 reads bus (41:ffcc) eor $dd00 II- - (bit 2-0 is now double inverted = correct) II- - 1541 C64 1541 C64 II- - bit5=data->bit7 bit4=clock->bit6 ----II> fbe5 *lsr 2 bit7->bit6 6->5 5->4 4->3 3->2 2->1 lsr II- - II- fbe6 *lsr 2 bit6->bit5 5->4 4->3 4->2 2->1 1->0 lsr II- - II- fbe7 *eor $a4 3 inverts bit 2-0 pin M & VIC-banc eor $a4 II- - II- - II- fbe9 *eor $dd00 4 reads bus (41:ffd3) eor $dd00 II- - (bit 2-0 is now double inverted = correct) II- - 1541 C64 1541 C64 II- - bit7=data->bit7 bit6=clock->bit6 ----II> fbec *sta $a4 3 stores IECIN byte sta $a4 II- - II- - II- fbee *pla 4 (restores D=A, pin M, VIC-banc) pla II- - II- - II- - II- fbef *bit $dd00 4 data->plus/minus-, clock->overflow-flag bit dd00 II- - (41:ffdb) II- - II- - II- fbf2 *sta $dd00 4 sets data = active (41:ffde) sta $dd00 II- - II- - II- - ----AI> (C64 IECIN) = 1541 IECOUT==================================================== -IA ff88 *stx $1800 4 sets clock = inactive (64:fbb4) lownibble -II -II ffaa *sta $4b 3 stores highnibble -II -II -II ffac *txa 2 IECOUT byte -II -II ffad *and #$0f 2 mascs lownibble -II -II ffaf *tax 2 -II -II ffb0 *lda $ea1d,x 4 nibble table (inverted, because C64 inputs are not -II loads low nibble inverted) -II -II -II ffb3 *ldx $7a 3 -II -II -II ffb5 *stx $1800 4 no function at IECOUT (only at LOAD)? -II -II data bit0 -> clock (64:fbd5) -II -II <10 -10 ffc0 *asl 2 -10 -10 ffc1 *and #$0f 2 clears bit 4 (ATNack=inactive) -10 -10 ffc3 *nop 2 -10 -10 ffc4 *sta $1800 4 bit3 -> data bit2 -> clock (64:fbdb) -10 -10 <32---- -32 ffc7 *ldx $4b 3 highnibble -32 -32 -32 ffc9 *lda $ea1d,x 4 nibble table -32 -32 -32 -32 ffcc *sta $1800 4 bit5 -> data bit4 -> clock (64:fbe2) -32 -32 <54---- -54 ffcf *asl 2 -54 -54 ffd0 *and #$0f 2 clears bit 4 (ATNack=inactive) -54 -54 ffd2 *iny 2 #$ff->#$00 -54 -54 ffd3 *sta $1800 4 bit7 -> data bit6 -> clock (64:fbe9) -54 -54 <76---- -76 ffd6 *bne $ffa3 2/3 never branches at IECOUT (only for LOAD) -76 -76 ffd8 *nop 2 -76 -76 ffd9 *lda $44 3 noEOI: data=inactive,clock=active %0xx01101 -76 EOI: data=active,clock=inactive %0xx00011 -76 -76 ffdb *sta $1800 4 noEOI: sets D=I, C=A (64:fbef) -76 -76 -IA -IA ffde *cmp $1800 4 (64:fbf2) -IA noEOI: waits until C64 sets data = active -IA EOI: doesn't wait because C64 sets clock = inactive? plus/minus II- fb41 *bpl $fb3e waits until 1541 sets data = inactive (41:ffb5) II- fb43 *sec II- - II- fb44 *lda $d012 4 VIC rasterbar lda $d012 II- - II- - II- - II- fb47 *sbc $b1 3 bit 2-0 = vertical softscroll register sbc $b1 II- - II- - II- fb49 *bcc $fb4f 2/3 b.i.in border (rasterbar 0-49 or 256-305, no badlines) II- - II- fb4b *and #$07 2 mascs bit 2-0, that 8 rasterbars remain and #$07 II- - (data=inactive,clock=inactive,ATN=inactive) II- fb4d *beq $fb44 2/3 b.i. too few time until next badline beq $fb4d II- - II- fb4f *lda $b2 3 restores pin M and VIC-bank lda $b2 II- - (data=inactive,clock=inactive) II- - II- fb51 *stx $dd00 4 data=active,clock=inactive,ATN=inactive stx $dd00 II- - (41:ffb8) II- - II- - put 1541 paper arrow here (late/ealy) ----AI> fb54 *bit $dd00 4 clock -> overflow bit $dd00 AI- - AI- - AI- - ----AI> fb57 *bvc $faf0 2 b.i. 1541 sets clock = active (41:ffdb) bvc $faf0 AI- - =b.i. 1541 must load next block from disk AI- fb59 *nop 2 nop AI- - AI- fb5a *sta $dd00 4 sets data = inactive sta $dd00 AI- - AI- - AI- - ----II> fb5d *ora $dd00 4 reads bus (41:ffbd) ora $dd00 II- - II- - 1541 C64 1541 C64 II- - bit1=data->bit7 bit0=clock->bit6 ----II> fb60 *lsr 2 bit7->bit6 bit6->bit5 lsr II- - II- fb61 *lsr 2 bit6->bit5 bit5->bit4 lsr II- - II- fb62 *nop 2 nop II- - II- fb63 *ora $dd00 4 reads bus (41:ffc4) ora $dd00 II- - II- - 1541 C64 1541 C64 II- - bit3=data->bit7 bit2=clock->bit6 ----II> fb66 *lsr 2 bit7->bit6 bit6->bit5 5->4 4->3 lsr II- - II- fb67 *lsr 2 bit6->bit5 bit5->bit4 4->3 4->2 lsr II- - II- fb68 *eor $b2 3 inverts bit 2-0 (pin M & VIC-bank) eor $b2 II- - II- - II- fb6a *eor $dd00 4 reads bus (41:ffcc) eor $dd00 II- - (bit 2-0 is now double inverted = correct) II- - 1541 C64 1541 C64 II- - bit5=data->bit7 bit4=clock->bit6 ----II> fb6d *lsr 2 bit7->bit6 6->5 5->4 4->3 3->2 2->1 lsr II- - II- fb6e *lsr 2 bit6->bit5 5->4 4->3 4->2 2->1 1->0 lsr II- - II- fb6f *eor $b2 3 inverts bit 2-0 (pin M & VIC-bank) eor $b2 II- - II- - II- fb71 *eor $dd00 4 reads bus (41:ffd3) eor $dd00 II- - (bit 2-0 is now double inverted = correct) II- - 1541 C64 1541 C64 II- - bit5=data->bit7 bit4=clock->bit6 ----II> (C64 JIFFYDOS-LOAD) = 1541 JIFFYDOS-LOAD===================================== -AI ffb5 *stx $1800 4 sets data=inactive clock=inactive (64:fb3e) data bit0 -> clock (64:fb5d) -II -II <10 -10 ffc0 *asl 2 -10 -10 ffc1 *and #$0f 2 clears bit 4 (ATNack=inactive) -10 -10 ffc3 *nop 2 -10 -10 ffc4 *sta $1800 4 bit3 -> data bit2 -> clock (64:fb63) -10 -10 <32---- -32 ffc7 *ldx $4b 3 highnibble -32 -32 -32 ffc9 *lda $ea1d,x 4 nibble table -32 -32 -32 -32 ffcc *sta $1800 4 bit5 -> data bit4 -> clock (64:fb6a) -32 -32 <54---- -54 ffcf *asl 2 -54 -54 ffd0 *and #$0f 2 clears bit 4 (ATNack=inactive) -54 -54 ffd2 *iny 2 #$ff->#$00 -54 -54 ffd3 *sta $1800 4 bit7 -> data bit6 -> clock (64:fb71) -54 -54 <76---- -76 ffd6 *bne $ffa3 2/3 b.i. still bytes in buffer to transfer -76 -76 ffd8 *nop 2 -76 -76 ffd9 *lda $44 3 (clock=active) %0xx01101 -76 -76 -76 ffdb *sta $1800 4 sets data=inactive, clock=active (64:fb54) -76 -76 -IA -IA ffde *cmp $1800 4 waits until C64 sets data = active (64:fb51) -IA -IA